1. Field of the Invention
The present invention relates to a solid-state imaging device, a method of driving the solid-state imaging device, and a camera apparatus. More particularly, the present invention relates to an X-Y address type solid-state imaging device typified by a MOS-type solid-state imaging device, a method of driving the solid-state imaging device, and a camera apparatus (image-capturing apparatus) that uses the solid-state imaging device as an image-capturing device.
2. Description of the Related Art
In an X-Y address type solid-state imaging device, for example, a MOS-type solid-state imaging device, in order to microfabricate unit pixels, a selection transistor for selecting a pixel is omitted, and a pixel is selected by controlling the electrical potential of a floating diffusion section (hereinafter referred to as an “FD section”) by a resetting transistor for resetting the FD section, so that the unit pixel is realized by three transistors (see, for example, Japanese Unexamined Patent Application Publication No. 2002-51263, in particular, paragraph numbers 0010 to 0012, and FIG. 1).
The configuration of a pixel circuit of three transistors is shown in FIG. 15. As can be seen from FIG. 15, a unit pixel 100 includes an optoelectric transducer (here, photodiode) 101, a transfer transistor 102, an amplifier transistor 103, and a resetting transistor 104. A large number of unit pixels 100 are arranged two-dimensionally in a matrix on a semiconductor substrate.
As is clear from the above-described configuration, in the pixel circuit of three transistors, a selection transistor does not exist, and the pixel is selected by controlling the electrical potential of an FD section 105 by the resetting transistor 104. That is, for a non-selection pixel, the electrical potential of the FD section 105 is brought into a low level (hereinafter referred to as an ““L” level”), and for a selection pixel, the electrical potential of the FD section 105 is brought into a high level (hereinafter referred to as an ““H” level”), thereby outputting a signal of the selection pixel to a vertical signal line 107. Thereafter, by returning the electrical potential of the FD section 105 of the selection pixel to an “L” level, the pixel is returned to a non-selection state. This operation is performed simultaneously on pixels for one line.
In the pixel circuit of three transistors of the above-described configuration, the drain side of an amplifier transistor 103 is simply connected to power-supply wiring, and the drain side of the resetting transistor 104 is connected to drain wiring 108 which extends in the row direction (horizontal direction). In comparison, as shown in FIG. 16, as a result of adopting a configuration in which the drain side of the amplifier transistor 103 and the drain side of the resetting transistor 104 are connected commonly to the drain wiring, a contact, a diffusion layer, and wiring in the unit pixel 100 can be reduced. Thus, this is advantageous when the unit pixel 100 is formed more finely.
Although the drain wiring is not shown in FIG. 16, similarly to the case of FIG. 15, in the case of drain wiring extending in the row direction, the number of wirings extending in the row direction is three, and the number of wirings extending in the column direction (vertical direction) is one. As a result, it is difficult to form an opening for receiving incident light into the pixel, into a shape close to a square. Furthermore, since the electrical current of all the vertical signal lines 107 is supplied from one drain wiring, and large electrical current flows through the drain wiring, wiring resistance and wiring reliability become problems. These problems can be avoided by forming the drain wiring as wiring in the vertical direction or in a lattice form.
A description will now be given of a case in which the solid-state imaging device of the pixel configuration of FIG. 16 is driven. In the period other than the pixel reading (non-reading period), there are cases in which the drain wiring is brought into an “H” level and an “L” level. When the drain wiring is brought into an “L” level, there is a problem in that electrons leak from the drain wiring to the optoelectric transducer 101 via the resetting transistor 104 and the transfer transistor 102. Therefore, in the period other than the pixel reading, a driving method in which the drain wiring is brought into an “H” level is often adopted.
As described above, in a case where a driving method in which the drain wiring is brought into an “H” level in a period other than pixel reading is adopted, the timing relationship among the driving pulses, that is, a drain voltage DRN, a reset pulse RST, and a transfer pulse TRF, of the selection row in the pixel reading period, is shown in FIG. 17. In the timing chart of FIG. 17, a time t101 indicates a timing at which a reset level is received, and a time t102 indicates a timing at which a signal level is received.
In the non-selection row, the drain voltage DRN is provided in common, but the reset pulse RST and the transfer pulse TRF are not provided. The drain voltage DRN is usually placed at an “H” level (power-supply voltage). The electrical potential of the FD section 105 is at an “L” level for all the rows. When the reset pulse RST is provided to the selection row, the resetting transistor 104 is turned on, causing the electrical potential of the FD section 105 of the selection row to be placed at an “H” level. Consequently, the level when the selection row is reset, that is, the reset level, is output to the vertical signal line 107 through the amplifier transistor 103. This reset level is received at the circuit at the next stage.
Next, when the transfer pulse TRF is provided, the transfer transistor 102 is turned on, causing photoelectrons to be transferred from the optoelectric transducer 101 to the FD section 105 of the selection row. Then, the level of the FD section 105, which corresponds to the photoelectrons, that is, the signal level, is output to the vertical signal line 107 through the amplifier transistor 103. This signal level is received at the circuit at the next stage.
Thereafter, the drain wiring is placed at 0 V, and after the FD section 105 of the selection row is returned to the “L” level by providing the reset pulse RST, the drain wiring is returned to the “H” level (hereinafter referred to as a “backfilling operation”). A series of periods in which a pixel is made to operate in this manner is herein referred to as a reading period. In this reading period, by calculating the difference between the reset level and the signal level at the circuit at the next stage, a signal (pixel signal) corresponding to the amount of light photoreceived by the optoelectric transducer 101 can be obtained.
The inventors of the present invention test-produced a solid-state imaging device of the pixel configuration of FIG. 2. Then, the inventors discovered that, in this type of solid-state imaging device, a lot of pixels with more dark current appear on a captured image. Furthermore, by analyzing this phenomenon, the inventors clarified that a large part of the above phenomenon can be described as described below.
A bias current flows through the vertical signal line 107 in a particular period even other than the pixel reading period. FIG. 4 is an illustration thereof. In FIG. 4, the horizontal ineffective period is mainly a period in which the pixel is made to operate so that the signal is received at the circuit of the next stage. The horizontal effective period is mainly a period in which the pixel signals are output in sequence from the circuit of the next stage.
In order to read a pixel of a particular row, a bias current needs to be made to flow. In FIG. 4, the n-th row reading period is the above-described reading period for the n-th row. Periods A and B are periods in which a bias current flows in a state in which any row is not read before and after that reading period. After the pixel signal of the n-th row is read into the circuit at the next stage, the supply of the bias current is shut off. Thereafter, after passing through a horizontal effective period in which signals for one line are output in sequence from the circuit of the next stage, the reading of the next row is performed similarly.
Here, in the periods A and B, any row is not in a reading state. At this time, due to the relationship of variations of the threshold values of the amplifier transistor 103 and the resetting transistor 104, the bias current flows to a pixel having the lowest channel voltage of the amplifier transistor 103 (hereinafter referred to as a “low channel pixel”) among a large number of pixels connected to the vertical signal line 107. In this connection, in the amplifier transistor 103 and the resetting transistor 104, since the threshold values are lowered to ensure an operation margin, a pixel for which electrical current cannot be shut off completely exists with respect to at least the variations.
An example of the distribution of low channel pixels of each column in the pixel section is shown in FIG. 18. In the periods A and B, electrical current flows through these low channel pixels. The potential of the amplifier transistor 103 of the pixel is shown in FIG. 19. The gate potential of the amplifier transistor 103 is at an “L” level. At this time, electrons flow into the drain wiring from the vertical signal line 107, and since the gate potential of the amplifier transistor 103 is at an “L” level, the potential difference at the drain end is large, and a high electric-field is applied.
When the electrons flow at this large potential difference, the electrons acquire large energy (these electrons are generally called “hot carriers”), part thereof is emitted to a P well, and photons are generated. The electrons and the photons jump into the optoelectric transducer 101 nearby, and dark current is formed. That is, the dark current of the pixel corresponding to FIG. 18 is large, and the dark current is displayed as a white point on the image-capturing plane. In practice, a column in which a plurality of white points appear and a column in which there is no conspicuous white point exist depending on the distribution of variations and the state of the interface.
Reading of pixels is performed on all the rows while being scanned in sequence for each row. In the periods A and B, the foregoing occurs in the low channel pixels of each column with respect to each of the rows. Consequently, the dark current of the low channel pixel becomes particularly large. That is, for the low channel pixel, since this phenomenon occurs when the pixel itself is not a selection row, the dark current becomes large. The white point which occurs due to the above reasons is hereinafter referred to as a “non-selection hot carrier white point”).
In the pixel of the type in which the selection transistor is connected in series to the amplifier transistor 103, since the supply of the electrical current is completely shut off by that selection transistor also in the periods A and B, the problem of the non-selection hot carrier white point does not occur. In other words, the problem of the non-selection hot carrier white point is specific to the solid-state imaging device of the three-transistor-type pixel configuration having no selection transistor.